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19-0433; Rev 3; 4/03
Full-Featured P Supervisory Circuit with 1.5% Reset Accuracy
General Description
The MAX807 microprocessor (P) supervisory circuit reduces the complexity and number of components needed to monitor power-supply and battery-control functions in P systems. A 70A supply current makes the MAX807 ideal for use in portable equipment, while a 2ns chip-enable propagation delay and 250mA output current capability (20mA in battery-backup mode) make it suitable for larger, higher-performance equipment. The MAX807 comes in 16-pin DIP, SO, and TSSOP packages, and provides the following functions: * P reset. The active-low RESET output is asserted during power-up, power-down, and brownout conditions, and is guaranteed to be in the correct state for VCC down to 1V. * Active-high RESET output. * Manual-reset input. * Two-stage power-fail warning. A separate low-line comparator compares VCC to a threshold 52mV above the reset threshold. This low-line comparator is more accurate than those in previous P supervisors. * Backup-battery switchover for CMOS RAM, real-time clocks, Ps, or other low-power logic. * Write protection of CMOS RAM or EEPROM. * 2.275V threshold detector provides for power-fail warning and low-battery detection, or monitors a power supply other than +5V. * BATT OK status flag indicates that the backup-battery voltage is above +2.275V. * Watchdog-fault output--asserted if the watchdog input has not been toggled within a preset timeout period.
TOP VIEW
PFI 1 16 OUT 15 BATT OK 14 BATT
____________________________Features
o Precision 4.675V (MAX807L), 4.425V (MAX807M), or 4.575V (MAX807N) Voltage Monitoring o 200ms Power-OK/Reset Time Delay o RESET and RESET Outputs o Independent Watchdog Timer o 1A Standby Current o Power Switching 250mA in VCC Mode 20mA in Battery-Backup Mode o On-Board Gating of Chip-Enable Signals; 2ns CE Gate Propagation Delay o MaxCap(R) and SuperCap(R) Compatible o Voltage Monitor for Power Fail o Backup-Battery Monitor o Guaranteed RESET Valid to VCC = 1V o 1.5% Low-Line Threshold Accuracy 52mV above Reset Threshold
MAX807L/M/N
Pin Configuration
Applications
Computers Controllers Intelligent Instruments Critical P Power Monitoring Portable/Battery-Powered Equipment
PFO 2 VCC 3 WDI 4
MAX807
13 BATT ON 12 CE IN 11 CE OUT 10 WDO 9 RESET
GND 5 MR LOW LINE RESET 6 7 8
DIP/SO/TSSOP
Ordering Information and Typical Operating Circuit appear at end of data sheet. SuperCap is a registered trademark of Baknor Industries. MaxCap is a registered trademark of Cesiwid, Inc. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Full-Featured P Supervisory Circuit with 1.5% Reset Accuracy MAX807L/M/N
ABSOLUTE MAXIMUM RATINGS
Input Voltages (with respect to GND) VCC ..........................................................................-0.3V to 6V VBATT .......................................................................-0.3V to 6V All Other Inputs......................................-0.3V to (VOUT + 0.3V) Input Current VCC Peak ...........................................................................1.0A VCC Continuous .............................................................500mA IBATT Peak......................................................................250mA IBATT Continuous .............................................................50mA GND .................................................................................50mA All Other Inputs ................................................................50mA Continuous Power Dissipation (TA = +70C) Plastic DIP (derate 10.53mW/C above +70C) ..........842mW Wide SO (derate 9.52mW/C above +70C)................762mW CERDIP (derate 10.00mW/C above +70C) ...............800mW TSSOP (derate 6.70 mW/C above +70C) .................533mW Operating Temperature Ranges MAX807_C_E ......................................................0C to +70C MAX807_E_E ...................................................-40C to +85C MAX807_MJE ................................................-55C to +125C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V CC = 4.60V to 5.5V for the MAX807L, V CC = 4.50V to 5.5V for the MAX807N, V CC = 4.35V to 5.5V for the MAX807M, VBATT = 2.8V, VPFI = 0V, TA = TMIN to TMAX. Typical values are tested with VCC = 5V and TA = +25C, unless otherwise noted.) PARAMETER Operating Voltage Range VBATT, VCC (Note 1) IOUT = 25mA VOUT in Normal Operating Mode VCC = 4.5V SYMBOL CONDITIONS MIN 0 VCC - 0.02 TYP MAX 5.5 UNITS V
IOUT = 250mA, VCC - 0.35 VCC - 0.22 MAX807C/E IOUT = 250mA, VCC - 0.45 MAX807M
V
VCC to OUT On-Resistance
VOUT in Battery-Backup Mode
BATT to OUT On-Resistance Supply Current in Normal Operating Mode (excludes IOUT) Supply Current in BatteryBackup Mode (excludes IOUT) (Note 2)
VCC = 3V, VBATT = 2.8V, IOUT = 100mA MAX807C/E VCC = 4.5V, IOUT = 250mA MAX807M VCC = 3V, IOUT = 100mA VBATT = 4.5V, IOUT = 20mA, VCC = 0V VBATT = 2.8V, IOUT = 10mA, VCC = 0V VBATT = 2.0V, IOUT = 5mA, VCC = 0V VBATT = 4.5V, IOUT = 20mA VBATT = 2.8V, IOUT = 10mA VBATT = 2.0V, IOUT = 5mA
VCC - 0.25 VCC - 0.12 1.0 1.2 VBATT - 0.17 VBATT - 0.25 VBATT - 0.12 VBATT - 0.20 VBATT - 0.08 8.5 12 16 70
1.4 1.8 2.5
V
25 40 110 1 5 50 0.1
A
VCC = 0V, VBATT = 2.8V
TA = +25C MAX807C/E MAX807M TA = +25C -0.1 -1.0
0.4
A
BATT Standby Current (Note 3)
VBATT = 2.8V, VCC = 3.0V
TA = TMIN to TMAX Power up Power down
A 1.0 VBATT + 0.05 VBATT 50 0.1 2.7 V mV V V
Battery-Switchover Threshold Battery-Switchover Hysteresis BATT ON Output, Low Voltage BATT ON Output, High Voltage 2
VBATT = 2.8V
VRST (max), ISINK = 3.2mA VCC = 0V, ISOURCE = 0.1mA, VBATT = 2.8V
0.4
2
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Full-Featured P Supervisory Circuit with 1.5% Reset Accuracy
ELECTRICAL CHARACTERISTICS (continued)
(V CC = 4.60V to 5.5V for the MAX807L, V CC = 4.50V to 5.5V for the MAX807N, V CC = 4.35V to 5.5V for the MAX807M, VBATT = 2.8V, VPFI = 0V, TA = TMIN to TMAX. Typical values are tested with VCC = 5V and TA = +25C, unless otherwise noted.) PARAMETER BATT ON Output Short-Circuit Current SYMBOL CONDITIONS MIN TYP 70 5 4.600 4.500 4.350 4.675 4.575 4.425 13 52 4.73 4.63 4.48 26 24 140 1.12 VIL = 0.8V, VIH = 0.75 x VCC VCC = 1V, MAX807_C VCC = 1.2V, MAX807_E/M VCC - 1.5 0.1 VCC - 0.1 60 1.6 100 0.3 0.3 0.4 V 200 1.6 280 2.24 4.750 4.650 4.500 MAX UNITS mA Sink current Source current, VCC = 0V, VBATT = 2.8V RESET, LOW LINE, AND WATCHDOG TIMER MAX807L MAX807N Reset Threshold VRST VCC rising and falling MAX807M Reset Threshold Hysteresis LOW LINE to RESET Threshold Voltage LOW LINE Threshold, VCC Rising VCC to RESET Delay VCC to LOW LINE Delay RESET Active-Timeout Period Watchdog-Timeout Period Minimum Watchdog Input Pulse Width tRP tWD VLR VCC falling MAX807L MAX807N MAX807M VCC falling at 1mV/s VCC falling at 1mV/s VCC rising
MAX807L/M/N
V mV
30
70 4.81 4.71 4.56
mV
VLL
V s s ms s ns
RESET Output Voltage
ISINK = 50A, VBATT = 0V, VCC falling
RESET Output Short-Circuit Current RESET Output Voltage RESET Output Short-Circuit Current LOW LINE Output Voltage LOW LINE Output Short-Circuit Current WDO Output Voltage WDO Output Short-Circuit Current WDI Threshold Voltage (Note 4) WDI Input Current
ISC
ISC
ISC
ISC VIH VIL VIH
ISINK = 3.2mA, VCC = 4.25V ISOURCE = 0.1mA Output sink current, VCC = 4.25V Output source current ISINK = 3.2mA ISOURCE = 5mA Output sink current Output source current, VCC = 4.25V ISINK = 3.2mA, VCC = 4.25V ISOURCE = 5mA Output sink current, VCC = 4.25V Output source current ISINK = 3.2mA ISOURCE = 5mA Output sink current Output source current
mA 0.4 V mA 0.4 V mA 0.4 V mA V A
VCC - 1.5 60 15 VCC - 1.5 28 20 VCC - 1.5 35 20 0.75 x VCC 0.8
Reset deasserted, WDI = 0V Reset deasserted, WDI = VCC
-50
-10 16
50
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3
Full-Featured P Supervisory Circuit with 1.5% Reset Accuracy MAX807L/M/N
ELECTRICAL CHARACTERISTICS (continued)
(V CC = 4.60V to 5.5V for the MAX807L, V CC = 4.50V to 5.5V for the MAX807N, V CC = 4.35V to 5.5V for the MAX807M, VBATT = 2.8V, VPFI = 0V, TA = TMIN to TMAX. Typical values are tested with VCC = 5V and TA = +25C, unless otherwise noted.) PARAMETER PFI Input Threshold PFI Hysteresis PFI Leakage Current PFI to PFO Delay (Note 5) CHIP-ENABLE GATING CE IN Leakage Current CE IN to CE OUT Resistance (Note 6) CE OUT Short-Circuit Current (RESET Active) CE IN to CE OUT Propagation Delay (Note 7) CE OUT Output Voltage High (RESET Active) RESET to CE OUT Delay MANUAL RESET INPUT MR Minimum Pulse Input MR-to-RESET Propagation Delay MR Threshold MR Pullup Current BATT OK COMPARATOR BATT OK Threshold BATT OK Hysteresis LOGIC OUTPUTS Output Voltage (PFO, BATT OK) Output Short-Circuit Current VBOK VIH VIL MR = 0V 2.4 0.8 50 2.200 100 2.265 20 200 2.350 1 170 s ns V A V mV Disabled mode, MR = 0V Enabled mode, VCC = VRST (max) VCC = 5V, disabled mode, CE OUT = 0, MR = 0V VCC = 5V, CLOAD = 50pF, 50 source impedance driver VCC = 5V, IOUT = 2mA VCC = 0V, IOUT = 10A 3.5 V VBATT - 0.1 VBATT 28 s 0.00002 75 17 2 8 1 150 A mA ns VOD = 30mV, VPFI falling SYMBOL VPFT VPFI falling VPFI rising CONDITIONS MIN 2.20 2.22 TYP 2.265 2.285 20 0.005 14 MAX 2.33 2.35 40 UNITS V mV nA s
Disabled mode, MR = 0V
VCC falling
VOL VOH ISC
ISINK = 3.2mA ISOURCE = 5mA Output sink current Output source current
0.4 VCC - 1.5 35 20
V mA
Note 1: Either VCC or VBATT can go to 0 if the other is greater than 2.0V. Note 2: The supply current drawn by the MAX807 from the battery (excluding IOUT) typically goes to 15A when (VBATT - 0.1V) < VCC < VBATT. In most applications, this is a brief period as VCC falls through this region (see Typical Operating Characteristics). Note 3: "+"= battery discharging current, "-"= battery charging current. Note 4: WDI is internally connected to a voltage-divider between VCC and GND. If unconnected, WDI is driven to 1.8V (typical), disabling the watchdog function. Note 5: Overdrive (VOD) is measured from center of hysteresis band. Note 6: The chip-enable resistance is tested with V CE IN = VCC/2, and I CE IN = 1mA. Note 7: The chip-enable propagation delay is measured from the 50% point at CE IN to the 50% point at CE OUT.
4
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Full-Featured P Supervisory Circuit with 1.5% Reset Accuracy
__________________________________________Typical Operating Characteristics
(VCC = 5V, VBATT = 2.8V, PFI = 0, no load, TA = +25C, unless otherwise noted.)
MAX807L/M/N
VCC SUPPLY CURRENT vs. TEMPERATURE (NORMAL OPERATING MODE)
78 VCC SUPPLY CURRENT (A) 76 74 72 70 68 66 64 62 60 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (C) 0
MAX807-01
BATTERY SUPPLY CURRENT vs. TEMPERATURE (BATTERY-BACKUP MODE)
MAX807-02
CHIP-ENABLE PROPAGATION DELAY vs. TEMPERATURE
MAX807-03
80
3.0 BATTERY SUPPLY CURRENT (A) 2.5
6 5 PROPAGATION DELAY (ns) 4 3 2 1 0
2.0 1.5 1.0 0.5
-60 -40 -20 0
20 40 60 80 100 120 140
-60 -40 -20 0
20 40 60 80 100 120 140
TEMPERATURE (C)
TEMPERATURE (C)
BATT-TO-OUT ON-RESISTANCE vs. TEMPERATURE
MAX807-04
MAX807-05
BATT-TO-OUT ON-RESISTANCE ()
VCC = 0V IOUT = 10mA 25 VBATT = 2.0V
VCC-TO-OUT ON-RESISTANCE ()
1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7
IOUT = 250mA
2.320 PFI THRESHOLD (V) 2.300 2.280 2.260 2.240 2.220 2.200
20
15
VBATT = 2.8V
10 VBATT = 4.5V 5 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (C)
-60 -40 -20 0
20 40 60 80 100 120 140
-60 -40 -20 0
20 40 60 80 100 120 140
TEMPERATURE (C)
TEMPERATURE (C)
RESET THRESHOLD vs. TEMPERATURE
MAX807-07
RESET TIMEOUT PERIOD vs. TEMPERATURE (VCC RISING)
MAX807-08
LOW LINE -TO-RESET THRESHOLD vs. TEMPERATURE (VCC FALLING)
LOW LINE-TO-RESET THRESHOLD (mV) 70 60 50 40 30 20 10 0 -60 -40 -20 0 20 40 60 80 100 120 140
MAX807-09
4.70 4.65 RESET THRESHOLD (V) 4.60 4.55 4.50 4.45 4.40 -60 -40 -20 0 MAX807M MAX807N
280 260 RESET TIMEOUT PERIOD (ms) 240 220 200 180 160 140 -60 -40 -20 0
80
MAX807L
20 40 60 80 100 120 140
20 40 60 80 100 120 140
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
_______________________________________________________________________________________
MAX807-06
30
VCC-TO-OUT ON-RESISTANCE vs. TEMPERATURE
1.6 2.340
PFI THRESHOLD vs. TEMPERATURE (VPFI FALLING)
5
Full-Featured P Supervisory Circuit with 1.5% Reset Accuracy MAX807L/M/N
Typical Operating Characteristics (contiued)
(VCC = 5V, VBATT = 2.8V, PFI = 0, no load, TA = +25C, unless otherwise noted.)
LOW LINE THRESHOLD vs. TEMPERATURE (VCC RISING)
MAX807-10
LOW LINE COMPARATOR PROPAGATION DELAY vs. TEMPERATURE (VCC FALLING)
MAX807-11
RESET COMPARATOR PROPAGATION DELAY vs. TEMPERATURE (VCC FALLING)
RESET COMPARATOR PROP DELAY (s) 35 30 25 20 15 10 5 0 -60 -40 -20 0 20 40 60 80 100 120 140 VCC FALLING AT 1mV/s
MAX807-12
4.80 4.75 LOW LINE THRESHOLD (V) 4.70 4.65 4.60 4.55 4.50 4.45 4.40 -60 -40 -20 0 M VERSION N VERSION L VERSION
40 LOW LINE COMPARATOR PROP DELAY (s) 35 30 25 20 15 10 5 0 -60 -40 -20 0 VCC FALLING AT 1mV/s
40
20 40 60 80 100 120 140
20 40 60 80 100 120 140
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
BATTERY CURRENT vs. INPUT SUPPLY VOLTAGE
MAX807-13
CHIP-ENABLE PROPAGATION DELAY vs. CE OUT LOAD CAPACITANCE
MAX807-14
BATT-TO-OUT vs. OUTPUT CURRENT
VCC = 0V SLOPE = 12
MAX807-15
16 14 BATTERY CURRENT (A) 12 10 8 6 4 2 0 2.5 2.6 2.7 VCC (V) 2.8 2.9
8
1000
PROPAGATION DELAY (ns)
6 BATT-TO-OUT (mV) 50 DRIVER 0 0 50 CLOAD (pF) 100
4
100
2
3.0
10 1 10 IOUT (mA) 100
VCC-TO-OUT vs. OUTPUT CURRENT
MAXIMUM TRANSIENT DURATION (s) SLOPE = 1.0
MAX807-16
MAXIMUM TRANSIENT DURATION vs. RESET COMPARATOR OVERDRIVE
MAX807-17
1000
1000
VCC - VOUT (mV)
100
100
RESET OCCURS
10
10
1 1 10 IOUT (mA) 100 1000
1 1 10 100 1000 RESET COMPARATOR OVERDRIVE (mV)
6
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Full-Featured P Supervisory Circuit with 1.5% Reset Accuracy
Pin Description
PIN 1 2 3 4 5 NAME PFI PFO VCC WDI GND FUNCTION Power-Fail Input. When PFI is less than VPFT (2.265V), PFO goes low. Connect to ground when unused. Power-Fail Output. This CMOS-logic output goes low when PFI is less than VPFT (2.265V). Valid for VCC 4V. PFO swings between VCC and GND. Input Supply Voltage, nominally +5V. Bypass with a 0.1F capacitor to GND. Watchdog Input. If WDI remains high or low longer than the watchdog-timeout period (1.6s, typ), WDO goes low. Leave unconnected to disable the watchdog function. Ground Manual-Reset Input. A logic low on MR asserts reset. Reset remains asserted as long as MR remains low and for 200ms after MR returns high. MR is an active-low input with an internal pullup to VCC. It can be driven using TTL or CMOS logic, or shorted to ground with a switch. Connect to VCC, or leave unconnected if not used. Low-Line Comparator Output. This CMOS-logic output goes low when VCC falls to 52mV above the reset threshold. Use this output to generate an NMI to initiate an orderly shutdown routine when VCC is falling. LOW LINE swings between VCC and GND. Active-High Reset Output. RESET is the inverse of RESET. It is a CMOS output that sources and sinks current. RESET swings between VCC and GND. Active-Low Reset Output. RESET is triggered and stays low when VCC is below the reset threshold or when MR is low. It remains low 200ms after VCC rises above the reset threshold or MR returns high. RESET has a strong pulldown but a relatively weak pullup, and can be wire-OR connected to logic gates. Valid for VCC 1V. RESET swings between VCC and GND. Watchdog Output. This CMOS-logic output goes low if WDI remains high or low longer than the watchdog-timeout period (tWD), and remains low until the next transition of WDI. WDO remains high if WDI is unconnected. WDO is high during reset. WDO swings between VCC and GND. Connect WDO to MR to generate resets during watchdog faults. Chip-Enable Output. Output to the chip-enable gating circuit. CE OUT is pulled up to the higher of VCC or VBATT, when the chip-enable gate is disabled. Chip-Enable Input Battery-On Output. CMOS-logic output/external bypass switch driver. High when OUT is connected to BATT and low when OUT is connected to VCC. Connect the base of a PNP transistor or gate of a PMOS transistor to BATT ON for IOUT requirements exceeding 250mA. BATT ON swings between the higher of VCC and VBATT and GND. Backup-Battery Input. When VCC falls below the reset threshold and VBATT, OUT switches from VCC to BATT. VBATT may exceed VCC. The battery can be removed while the MAX807 is powered-up, provided BATT is bypassed with a 0.1F capacitor to GND. If no battery is used, connect BATT to ground, and connect VCC and OUT together. Battery-OK Signal Output. High in normal operating mode when VBATT exceeds VBOK (2.265V). Valid for VCC 4V. Output Supply Voltage to CMOS RAM. When VCC exceeds the reset threshold or VCC > VBATT, OUT is connected to VCC. When VCC falls below the reset threshold and VBATT, OUT connects to BATT. Bypass OUT with a 0.1F capacitor to GND.
MAX807L/M/N
6
MR
7
LOW LINE
8
RESET
9
RESET
10
WDO
11 12
CE OUT CE IN
13
BATT ON
14
BATT
15
BATT OK
16
OUT
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7
Full-Featured P Supervisory Circuit with 1.5% Reset Accuracy MAX807L/M/N
Detailed Description
The MAX807 P supervisory circuit provides powersupply monitoring, backup-battery switchover, and program execution watchdog functions in P systems (Figure 1). Use of BiCMOS technology results in an improved 1.5% reset-threshold precision, while keeping supply currents typically below 70A. The MAX807 is intended for battery-powered applications that require high reset-threshold precision, allowing a wide powersupply operating range while preventing the system from operating below its specified voltage range.
RESET and RESET Outputs
The MAX807's RESET output ensures that the P powers up in a known state, and prevents code execution errors during power-down and brownout conditions. It accomplishes this by resetting the P, terminating program execution when VCC dips below the reset threshold or MR is pulled low. Each time RESET is asserted it stays low for the 200ms reset timeout period, which is set by an internal timer to ensure the P has adequate time to return to an initial state. Any time VCC goes below the reset threshold before the reset-timeout period is completed, the internal timer restarts. The watchdog timer can also initiate a reset if WDO is connected to MR (see the Watchdog Input section).
VCC OUT BATT BATTERY-BACKUP COMPARATOR P BATT ON RESET COMPARATOR N
LOW LINE LOW-LINE COMPARATOR WATCHDOG TRANSITION DETECTOR BATT OK PFO WDI VCC 50k POWER-FAIL COMPARATOR MR RESET RESET WDO THE HIGHER OF VCC OR VBATT P P CE IN N CE OUT
BATTERY-OK COMPARATOR GND PFI
STATE MACHINE OSCILLATOR
2.275V
MAX807
Figure 1. Block Diagram 8 _______________________________________________________________________________________
Full-Featured P Supervisory Circuit with 1.5% Reset Accuracy MAX807L/M/N
VRST VLL VCC VCC VRST + VLR VRST
VLOW LINE
VLOW LINE
VRESET
tRP
VRESET
(MAX801) VRESET (MAX808) VCE OUT
tRP
VRESET
VBATT SHOWN FOR VCC = 0 to 5V, VBATT = 2.8V, CE IN = GND
VCE OUT
VBATT SHOWN FOR VCC = 5V to 0, VBATT = 2.8V, CE IN = GND
Figure 2a. Timing Diagram, VCC Rising
Figure 2b. Timing Diagram, VCC Falling
The RESET output is active low and implemented with a strong pulldown/relatively weak pullup structure. It is guaranteed to be a logic low for 0 < VCC < VRST, provided VBATT is greater than 2V. Without a backup battery, RESET is guaranteed valid for VCC 1. It typically sinks 3.2mA at 0.1V saturation voltage in its active state. The RESET output is the inverse of the RESET output; it both sources and sinks current and cannot be wire-OR connected. Figure 2a shows a timing diagram with VCC rising and Figure 2b shows VCC falling.
MANUAL RESET MR
*
OTHER RESET SOURCES
MAX807
*
Manual Reset Input
Many P-based products require manual-reset capability to allow an operator or test technician to initiate a reset. The Manual Reset (MR) input permits the generation of a reset in response to a logic low from a switch, WDO, or external circuitry. Reset remains asserted while MR is low, and for 200ms after MR returns high. MR has an internal 50A to 200A pullup current, so it can be left open if it is not used. MR can be driven with TTL or CMOS-logic levels, or with open-drain/collector outputs. Connect a normally open momentary switch from MR to GND to create a manual-reset function; external debounce circuitry is not required. If MR is driven from long cables or if the device is used in a noisy environment, connect a 0.1F capacitor from MR to ground to provide additional noise immunity. As shown in Figure 3, diode-ORed connections can be used to allow manual resets from multiple sources. Figure 4 shows the reset timing.
*DIODES NOT REQUIRED ON OPEN-DRAIN OUTPUTS.
Figure 3. Diode "OR" Connections Allow Multiple Reset Sources to Connect to MR
Watchdog Timer
Watchdog Input The watchdog circuit monitors the P's activity. If the P does not toggle the watchdog input (WDI) within 1.6s, WDO goes low. The internal 1.6s timer is cleared and WDO returns high when reset is asserted or when a transition (low-to-high or high-to-low) occurs at WDI while RESET is high. As long as reset is asserted, the timer remains cleared and does not count. As soon as reset is released, the timer starts counting (Figure 5). Supply current is typically reduced by 10A when WDI is at a valid logic level.
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9
Full-Featured P Supervisory Circuit with 1.5% Reset Accuracy MAX807L/M/N
1s MIN MR 170ns RESET
Chip-Enable Signal Gating
The MAX807 provides internal gating of chip-enable (CE) signals to prevent erroneous data from corrupting the CMOS RAM in the event of a power failure. During normal operation, the CE gate is enabled and passes all CE transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The MAX807 uses a series transmission gate from the Chip-Enable Input (CE IN) to the Chip-Enable Output (CE OUT) (Figure 1). The 8ns (max) chip-enable propagation from CE IN to CE OUT enables the MAX807 to be used with most Ps. Chip-Enable Input CE IN is high impedance (disabled mode) while RESET is asserted. During a power-down sequence when VCC passes the reset threshold, the CE transmission gate disables and CE IN becomes high impedance 28s after reset is asserted (Figure 7). During a power-up sequence, CE IN remains high impedance (regardless of CE IN activity) until reset is deasserted following the reset-timeout period. In the high-impedance mode, the leakage currents into this input are 1A (max) over temperature. In the lowimpedance mode, the impedance of CE IN appears as a 75 resistor in series with the load at CE OUT. The propagation delay through the CE transmission gate depends on both the source impedance of the drive to CE IN and the capacitive loading on CE OUT
CE IN 0V CE OUT 28s TYP
Figure 4. Manual-Reset Timing Diagram
Watchdog Output WDO remains high if there is a transition or pulse at WDI during the watchdog-timeout period. WDO goes low if no transition occurs at WDI during the watchdogtimeout period. The watchdog function is disabled and WDO is a logic high when V CC is below the reset threshold or WDI is an open circuit. To generate a system reset on every watchdog fault, diode-OR connect WDO to MR (Figure 6). When a watchdog fault occurs in this mode, WDO goes low, which pulls MR low, causing a reset pulse to be issued. As soon as reset is asserted, the watchdog timer clears and WDO returns high. With WDO connected to MR, a continuous high or low on WDI will cause 200ms reset pulses to be issued every 1.6s.
VRST VCC tRP WDO MR
VCC 4.7k
MAX807
RESET TO P
RESET
WDO VCC tWD WDI RESET WDI WDO CONNECTED TO P INTERRUPT. tRP tWD tRP WDO
50s
Figure 5. Watchdog Timing Relationship 10
Figure 6. Generating a Reset on Each Watchdog Fault
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Full-Featured P Supervisory Circuit with 1.5% Reset Accuracy MAX807L/M/N
VRST MAX VCC RESET THRESHOLD CE IN
VCC
MAX807
CE OUT 28s 26s CE IN 26s 50 DRIVER RESET RESET GND CE OUT 50pF CLOAD
Figure 7. Reset and Chip-Enable Timing
Figure 8. CE Propagation Delay Test Circuit
(see the Chip-Enable Propagation Delay vs. CE OUT Load Capacitance graph in the Typical Operating Characteristics). The CE propagation delay is production tested from the 50% point on CE IN to the 50% point on CE OUT using a 50 driver and 50pF of load capacitance (Figure 8). For minimum propagation delay, minimize the capacitive load at CE OUT and use a low output-impedance driver. Chip-Enable Output In the enabled mode, the impedance of CE OUT is equivalent to 75 in series with the source driving CE IN. In the disabled mode, the 75 transmission gate is off and CE OUT is actively pulled to the higher of VCC or VBATT. This source turns off when the transmission gate is enabled.
4.5V to 5.5V REGULATOR CHOLD VCC LOW LINE
TO P NMI
MAX807
CHOLD > ILOAD x tSHDN VLR
GND
Low-Line Comparator
The low-line comparator monitors VCC with a threshold voltage typically 52mV above the reset threshold, with 13mV of hysteresis. Use LOW LINE to provide a nonmaskable interrupt (NMI) to the P when power begins to fall to initiate an orderly software shutdown routine. In most battery-operated portable systems, reserve energy in the battery provides ample time to complete the shutdown routine once the low-line warning is encountered, and before reset asserts. If the system must contend with a more rapid VCC fall time--such as when the main battery is disconnected, a DC-DC converter shuts down, or a high-side switch is opened during normal operation--use capacitance on the VCC line to provide time to execute the shutdown routine (Figure 9). First calculate the worst-case time required for the system to perform its shutdown routine. Then, with the
Figure 9. Using LOW LINE to Provide a Power-Fail Warning to the P
worst-case shutdown time, the worst-case load current, and the minimum low-line to reset threshold (VLR(min)), calculate the amount of capacitance required to allow the shutdown routine to complete before reset is asserted: CHOLD = (ILOAD x tSHDN) / VLR (min) where tSHDN is the time required for the system to complete the shutdown routine, and includes the VCC to low-line propagation delay; and where ILOAD is the current being drained from the capacitor, VLR is the lowline to reset threshold.
11
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Full-Featured P Supervisory Circuit with 1.5% Reset Accuracy MAX807L/M/N
VIN R1 PFI R2 VCC R1 PFO R2 MR GND VIN GND PFI VCC
MAX807
MAX807
PFO
VCC PFO
VCC PFO VL VTRIP VCC R1 0V VIN R1 + R2 R2 VTRIP VTRIP = VPFT WHERE VPFT = 2.265V VPFH = 20mV NOTE: VTRIP, VL ARE NEGATIVE. VH VIN
VTRIP = R2 (VPFT + VPFH) VL = R2 (VPFT)
( R1 + R2 ) - )
VCC - R1
1
1
(
) )
(
1 1 + R1 R2
a)
b)
R1 + R2 VH = (VPFT + VPFH) R2
(
Figure 10. Using the Power-Fail Comparator to Monitor an Additional Power Supply: a) VIN is Negative, b) VIN is Positive
FROM REGULATED SUPPLY 0.1F
Power-Fail Comparator
VCC OUT 0.1F P POWER POWER TO CMOS RAM
MAX807
BATT 2.8V P
a)
RESET LOW LINE WDI GND
RESET NMI I/O LINE
PFI is the noninverting input to an uncommitted comparator. If PFI is less than VPFT (2.265V), PFO goes low. The power-fail comparator is intended to monitor the preregulated input of the power supply, providing an early power-fail warning so software can conduct an orderly shutdown. It can also be used to monitor supplies other than 5V. Set the power-fail threshold with a resistor-divider, as shown in Figure 10. Power-Fail Input PFI is the input to the power-fail comparator. The typical comparator delay is 14s from VIL to VOL (power failing), and 32s from VIH to VOH (power being restored). If unused, connect this input to ground.
VCC 0.1F VOLTAGE REGULATOR
OUT 0.1F
P POWER POWER TO CMOS RAM
MAX807
BATT 2.8V P
PFI GND
RESET PFO WDI
RESET NMI I/O LINE
Power-Fail Output The Power-Fail Output (PFO) goes low when PFI goes below VPFT. It typically sinks 3.2mA with a saturation voltage of 0.1V. With PFI above VPFT, PFO is actively pulled to V CC . Connecting PFI through a voltagedivider to a preregulated supply allows PFO to generate an NMI as the preregulated power begins to fall (Figure 11b). If the preregulated supply is inaccessible, use LOW LINE to generate the NMI (Figure 11a). The LOW LINE threshold is typically 52mV above the reset threshold (see the Low-Line Comparator section).
b) Figure 11. a) If the preregulated supply is inaccessible, LOW LINE generates the NMI for the P. b) Use PFO to generate the P NMI if the preregulated supply is accessible. 12 ______________________________________________________________________________________
Full-Featured P Supervisory Circuit with 1.5% Reset Accuracy MAX807L/M/N
Table 1. Input and Output Status in Battery-Backup Mode
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME PFI PFO VCC WDI GND MR LOW LINE RESET RESET WDO CE OUT CE IN BATT ON BATT BATT OK OUT FUNCTION The power-fail comparator remains active in battery-backup mode for VCC 4V. The power-fail comparator remains active in battery-backup mode for VCC 4V. Below 4V, PFO is forced low. Battery switchover comparator monitors VCC for active switchover. WDI is ignored and goes high impedance Ground--0V reference for all signals MR is ignored Logic low Logic high; the open-circuit output voltage is equal to VCC. Logic low Logic high. The open-circuit output voltage is equal to VCC. Logic high. The open-circuit output voltage is equal to VBATT. High impedance Logic high. The open-circuit output voltage is equal to VBATT. Supply current is 1A maximum for VBATT 2.8V. Logic high when VBATT exceeds 2.285V. Valid for VCC 4V. Below 4V, BATT OK is forced low. OUT is connected to BATT through two internal PMOS switches in series.
MAX807
VCC P
CONTROL CIRCUITRY
OUT 0.1F
Backup-Battery Input The BATT input is similar to VCC, except the PMOS switch is much smaller. This input is designed to conduct up to 20mA to OUT during battery backup. The on-resistance of the PMOS switch is approximately 13. Figure 12 shows the two series pass elements between the BATT input and OUT that facilitate UL approval. VBATT can exceed VCC during normal operation without causing a reset. Output Supply Voltage The output supply (OUT) transfers power from VCC or BATT to the P, RAM, and other external circuitry. At the maximum source current of 250mA, VOUT will typically be 260mV below VCC. Decouple this terminal with a 0.1F capacitor.
BATT
P
P
BATT ON Output
Figure 12. VCC and BATT-to-OUT Switch
Battery-Backup Mode
Battery backup preserves the contents of RAM in the event of a brownout or power failure. With a backup battery installed at BATT, the MAX807 automatically switches RAM to backup power when VCC falls. Two conditions are required for switchover to battery-backup mode: 1) VCC must be below the reset threshold; 2) VCC must be below VBATT. Table 1 lists the status of inputs and outputs during battery-backup mode.
The battery on (BATT ON) output indicates the status of the internal battery switchover comparator, which controls the internal V CC and BATT switches. For V CC greater than V BATT (ignoring the small hysteresis effect), BATT ON typically sinks 3.2mA at 0.4V. In battery-backup mode, this output sources approximately 5mA. Use BATT ON to indicate battery switchover status, or to supply gate or base drive for an external pass transistor for higher current applications (see the Typical Operating Circuit).
______________________________________________________________________________________
13
Full-Featured P Supervisory Circuit with 1.5% Reset Accuracy MAX807L/M/N
BATT OK Output
The BATT OK comparator monitors the backup battery voltage, comparing it with a 2.265V reference (VCC 4V). BATT OK remains high as long as the backup battery voltage remains above 2.265V, signaling that the backup battery has sufficient voltage to maintain the memory of static RAM. When the battery voltage drops below 2.265V, the BATT OK output drops low, signaling that the backup battery needs to be changed. SuperCap (e.g., order of 0.47F) and a simple charging circuit as a backup source (Figure 13). Since VBATT can exceed VCC while VCC is above the reset threshold, there are no special precautions when using these P supervisors with a SuperCap.
Alternative Chip-Enable Gating
Using memory devices with CE and CE inputs allows the MAX807 CE loop to be bypassed. To do this, connect CE IN to ground, pull up CE OUT to OUT, and connect CE OUT to the CE input of each memory device (Figure 14). The CE input of each part then connects directly to the chip-select logic, which does not have to be gated by the MAX807.
Applications Information
The MAX807 is not short-circuit protected. Shorting OUT to ground, other than power-up transients such as charging a decoupling capacitor, may destroy the device. If long leads connect to the IC's inputs, ensure that these lines are free from ringing and other conditions that would forward bias the IC's protection diodes. There are two distinct modes of operation: 1) Normal Operating Mode, with all circuitry powered up. Typical supply current from VCC is 70A, while only leakage currents flow from the battery. 2) Battery-Backup Mode, where VCC is below VBATT and VRST. The supply current from the battery is typically less than 1A.
Adding Hysteresis to the Power-Fail Comparator
The power-fail comparator has a typical input hysteresis of 20mV. This is sufficient for most applications where a power-supply line is being monitored through an external voltage-divider (Figure 10). Figure 15 shows how to add hysteresis to the power-fail comparator. Select the ratio of R1 and R2 such that PFI sees 2.265V when VIN falls to the desired trip point (VTRIP). Resistor R3 adds hysteresis. It will typically be an order of magnitude greater than R1 or R2. The current through R1 and R2 should be at least 1A to ensure that the 25nA (max) PFI input current does not shift the trip point. R3 should be larger than 10k to prevent it from loading down the PFO pin. Capacitor C1 adds additional noise rejection.
Using SuperCaps or MaxCaps with the MAX807
BATT has the same operating voltage range as VCC, and the battery-switchover threshold voltage is typically VBATT when VCC is decreasing or VBATT + 0.06V when V CC is increasing. This hysteresis allows use of a
Rp* CE +5V OUT 1N4148 VCC CE IN CE OUT CE CE RAM 2 CE BATT 0.47F OUT RAM 1
MAX807 MAX807
GND GND *MAXIMUM Rp VALUE DEPENDS ON THE NUMBER OF RAMs. MINIMUM Rp VALUE IS 1k.
CE RAM 3 CE CE RAM 4 CE
ACTIVE-HIGH CE LINES FROM LOGIC
Figure 13. SuperCap or MaxCap on BATT 14
Figure 14. Alternate CE Gating
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Full-Featured P Supervisory Circuit with 1.5% Reset Accuracy
Backup-Battery Replacement
The backup battery may be disconnected while VCC is above the reset threshold, provided BATT is bypassed with a 0.1F capacitor to ground. No precautions are necessary to avoid spurious reset pulses.
START
MAX807L/M/N
Negative-Going VCC Transients
While issuing resets to the P during power-up, powerdown, and brownout conditions, these supervisors are relatively immune to short-duration negative-going VCC transients (glitches). It is usually undesirable to reset the P when VCC experiences only small glitches. The Typical Operating Characteristics show Maximum Transient Duration vs. Reset Comparator Overdrive, for which reset pulses are not generated. The graph was produced using negative-going VCC pulses, starting at 5V and ending below the reset threshold by the magnitude indicated (reset comparator overdrive). The graph shows the maximum pulse width that a negative-going V CC transient may typically have without causing a reset pulse to be issued. As the amplitude of the transient increases (i.e., goes farther below the reset threshold), the maximum allowable pulse width decreases. Typically, a VCC transient that goes 40mV below the reset threshold and lasts for 3s or less will not cause a reset pulse to be issued.
VIN R1 VCC PFI C1* R3 R2 PFO GND TO P +5V PFO 0V 0V R1 + R2 VTRIP = 2.265 R2 VH = 2.265 / R2 || R3 R1 + R2 || R3 VL VTRIP VH VIN *OPTIONAL
SET WDI LOW SUBROUTINE OR PROGRAM LOOP, SET WDI HIGH
RETURN
END
Figure 16. Watchdog Flow Diagram
A 0.1F bypass capacitor mounted close to the VCC pin provides additional transient immunity.
Watchdog Software Considerations
To help the watchdog timer keep a closer watch on software execution, you can use the method of setting and resetting the watchdog input at different points in the program, rather than "pulsing" the watchdog input highlow-high or low-high-low. This technique avoids a "stuck" loop where the watchdog timer continues to be reset within the loop, keeping the watchdog from timing out. Figure 16 shows an example flow diagram where the I/O driving the watchdog input is set high at the beginning of the program, set low at the beginning of every subroutine or loop, then set high again when the program returns to the beginning. If the program should "hang" in any subroutine, the I/O is continually set low and the watchdog timer is allowed to time out, causing a reset or interrupt to be issued.
+5V
MAX807
Maximum VCC Fall Time
The VCC fall time is limited by the propagation delay of the battery switchover comparator and should not exceed 0.03V/s. A standard rule for filter capacitance on most regulators is on the order of 100F per amp of current. When the power supply is shut off or the main battery is disconnected, the associated initial VCC fall rate is just the inverse or 1A / 100F = 0.01V/s. The VCC fall rate decreases with time as VCC falls exponentially, which more than satisfies the maximum fall-time requirement.
15
VL - 2.265 + 5 - 2.265 = 2.265 R1 R3 R2
Figure 15. Adding Hysteresis to the Power-Fail Comparator
______________________________________________________________________________________
Full-Featured P Supervisory Circuit with 1.5% Reset Accuracy MAX807L/M/N
Typical Operating Circuit
PART
+5V 0.1F 0.1F REALTIME CLOCK
Ordering Information
TEMP RANGE 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -55C to +125C PIN-PACKAGE 16 Plastic DIP 16 TSSOP 16 Wide SO 16 Plastic DIP 16 TSSOP 16 Wide SO 16 CERDIP MAX807_CPE MAX807_CUE MAX807_CWE MAX807_EPE MAX807_EUE MAX807_EWE MAX807_MJE
VCC BATT ON OUT BATT 0.47F* CE OUT OTHER SYSTEM RESET SOURCES PUSHBUTTON SWITCH MR CE IN
CMOS RAM
ADDRESS DECODE A0-A15 I/O NMI RESET RESET INTERRUPT +12V SUPPLY FAILURE WATCHDOG FAILURE
This part offers a choice of reset threshold voltage. From the table below, select the suffix corresponding to the desired threshold and insert it into the blank to complete the part number.
P
MAX807
WDI LOW LINE RESET RESET BATT OK PFO PFI GND WDO
SUFFIX L N M
RESET THRESHOLD (V) MIN 4.60 4.50 4.35 TYP 4.675 4.575 4.425 MAX 4.75 4.65 4.50
+12V SUPPLY
*MaxCap.
___________________Chip Information
TRANSISTOR COUNT: 984
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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